Python Reference Documentation

Board Driver

Boards Module

This Module contains the Board Driver class which is the entry point to drive the Firmware functionalities.

This module init script contains factory methods to create a Board Driver instance based on the target configuration.

For Example:

• getGeccoUARTDriver() returns a Driver configured for the Gecco Target connected via UART
• getGeccoNODriver() returns a Board Driver without I/O, or a dummy IO layer - useful to test scripts without a Hardware connected

BoardDriver

Source code in drivers/boards/board_driver.py

class BoardDriver():

    def __init__(self,rfg):
        self.rfg = rfg
        self.houseKeeping = drivers.astep.housekeeping.Housekeeping(self,rfg)
        self.asics = []

        # Synchronisation Utils
        ########

        ## Opened Event -> Set/unset by close/open
        ## Useful to start or stop tasks dependent on open/close state of the driver
        self.openedEvent = asyncio.Event()

    def selectUARTIO(self,portPath : str | None = None ):
        """This method is common to all targets now, because all targets have a USB-UART Converter available"""
        if (portPath == None):
            import drivers.astep.serial
            port = drivers.astep.serial.selectFirstLinuxFTDIPort()
            if port:
                self.rfg.withUARTIO(port.device)
                return self
            else:
                raise RuntimeError("No Serial Port could be listed")
        else:
            self.rfg.withUARTIO(portPath)
            return self


    async def open(self):
        """Open the Register File I/O Connection to the underlying driver"""
        await self.rfg.io.open()
        self.openedEvent.set()

    async def close(self):
        """Close the Register File I/O Connection to the underlying driver"""
        self.openedEvent.clear()
        await self.rfg.io.close()

    async def waitOpened(self):
        await self.openedEvent.wait()

    def isOpened(self) -> bool: 
        return self.openedEvent.is_set()

    def debug_full(self):
        rfg.core.debug()

    def flush(self):
        """Flushed the RFG instance, use to be sure no bytes are pending writting"""
        self.rfg.flush()

    async def readFirmwareVersion(self):
        """Returns the raw integer with the firmware Version"""
        return (await (self.rfg.read_hk_firmware_version()))

    async def readFirmwareID(self):
        """Returns the raw integer with the firmware id"""
        return await (self.rfg.read_hk_firmware_id())

    async def readFirmwareIDName(self):
        """"""
        boards  =  {0xab02: 'Nexys GECCO Astropix v2',0xab03: 'Nexys GECCO Astropix v3',0xac03:"CMOD Astropix v3"}
        boardID =  await (self.readFirmwareID())
        return boards.get(boardID,"Firmware ID unknown: {0}".format(hex(boardID)))

    async def checkFirmwareVersionAfter(self,v):
        return await (self.readFirmwareVersion()) >= v

    def getFPGACoreFrequency(self):
        """Returns the Core Clock frequency to help clock divider configuration - this method is overriden by implementation class (Gecco or Cmod)"""
        pass

    ## Loopback Model
    ################
    def getLoopbackModelForLayer(self,layer):
        return Astropix3LBModel(self,layer)

    ## Chips
    ################
    async def setupASICSAuto(self, configFile : str ):

        #assert version >=2 and version < 4 , "Only Astropix 2 and 3 Supported"
        self.asics.clear()
        asic = Asic(rfg = self.rfg, row = 0)
        asic.chipversion = (await self.readFirmwareID()) & 0x0F
        print(configFile)
        self.asics.append(asic)

        return asic

    def setupASICS(self, version: int , rows: int = 1 , chipsPerRow:int = 1 , configFile : str | None = None):
        """Configure one or multiple rows with a single config file

        Args:
            version: int, AstroPix chip version
            rows: int, number of rows, default=1
            chipsPerRow: int, number of chips per row (aka daisy chain), default=1
            configFile: srt, path to yaml config file, defaults to None (no configuration applied?)
        """
        assert version >=2 and version < 4 , "Only Astropix 2 and 3 Supported"
        if version == 2: 
            self.geccoGetVoltageBoard().dacvalues =  (8, [0, 0, 1.1, 1, 0, 0, 1, 1.100])

        for i in range(rows):
            self.setupASIC(version, row=i, chipsPerRow=chipsPerRow, configFile=configFile)

    def setupASIC(self, version: int, row: int = 0, chipsPerRow: int=1, configFile: str|None = None):
        """Configures one row (aka daisy chain) with a single config file

        Args:
            version: int, AstroPix chip version
            row: int, number of the current row, default=0
            chipsPerRow: int, number of chips per row (aka daisy chain), default=1
            configFile: srt, path to yaml config file, defaults to None (no configuration applied?)
        """
        asic = Asic(rfg = self.rfg, row = row)
        asic.chipversion = version
        if configFile is not None: 
            asic.load_conf_from_yaml(configFile)
        asic._num_chips = chipsPerRow
        self.asics.append(asic)

    def getAsic(self,row = 0 ): 
        """Returns the Asic Model for the Given Row - Other chips in the Daisy Chain are handeled by the returned 'front' model"""
        return self.asics[row]

    async def enableSensorClocks(self,flush:bool = False):
        """Writes the I/O Control register to enable both Timestamp and Sample clock outputs"""
        await self.ioSetSampleClock(enable=True, flush=flush)
        await self.ioSetTimestampClock( enable=True, flush=flush)

    async def getIOControlRegister(self):
        return await self.rfg.read_io_ctrl()

    async def ioSetSampleClock(self,enable:bool,flush:bool = False):
        v = await self.rfg.read_io_ctrl()
        if enable: v|=0x1 
        else: v &= ~(0x1)
        await self.rfg.write_io_ctrl(v,flush) 

    async def ioSetTimestampClock(self,enable:bool,flush:bool = False):
        v = await self.rfg.read_io_ctrl()
        if enable: v|=0x2 
        else: v &= ~(0x2)
        await self.rfg.write_io_ctrl(v,flush) 

    async def ioSetSampleClockSingleEnded(self,enable:bool,flush:bool = False):
        v = await self.rfg.read_io_ctrl()
        if enable: v|=0x4 
        else: v &= ~(0x4)
        await self.rfg.write_io_ctrl(v,flush) 

    async def ioSetInjectionToChip(self,enable:bool = True,flush:bool = False):
        v = await self.rfg.read_io_ctrl()
        if enable: v &= ~(0x8)
        else: v |= 0x8
        await self.rfg.write_io_ctrl(v,flush) 


    async def ioSetFPGAExternalTSClockDifferential(self,enable:bool,flush:bool = False):
        """If an external clock input is used for the FPGA TS counter, it is differential or not"""
        v = await self.rfg.read_io_ctrl()
        if enable: v|=0x10 
        else: v &= ~(0x10)
        await self.rfg.write_io_ctrl(v,flush)

    async def ioSetAstropixTSToFPGATS(self,enable:bool,flush:bool = False):
        """The Astropix TS clock can be sourced from the external FPGA TS clock (it true) or from the internal TS clock (if false)"""
        v = await self.rfg.read_io_ctrl()
        if enable: v|=0x20 
        else: v &= ~(0x20)
        await self.rfg.write_io_ctrl(v,flush) 

    ## Layers
    ##################
    async def configureLayersFrameTag(self,enable, flush = False):
        await self.rfg.write_layers_cfg_frame_tag_counter_ctrl(1 if enable is True else 0,flush)

    async def configureLayersFrameTagFrequency(self, targetFrequencyHz : int , flush = False):
        """Calculated required divider to reach the provided target SPI clock frequency"""
        coreFrequency = self.getFPGACoreFrequency()
        divider = int( coreFrequency / ( targetFrequencyHz))
        assert divider >=1 and divider <=255 , (f"Divider {divider} is too high, min. clock frequency: {int(coreFrequency/255)}")
        await self.configureLayersFrameTagDivider(divider,flush)

    async def configureLayersFrameTagDivider(self, divider , flush = False):
        await self.rfg.write_layers_cfg_frame_tag_counter_trigger_match(divider,False)
        await self.rfg.write_layers_cfg_frame_tag_counter_trigger(0,flush)

    async def configureLayerSPIFrequency(self, targetFrequencyHz : int , flush = False):
        """Calculated required divider to reach the provided target SPI clock frequency"""
        coreFrequency = self.getFPGACoreFrequency()
        divider = int( coreFrequency / (2 * targetFrequencyHz))
        assert divider >=1 and divider <=255 , (f"Divider {divider} is too high, min. clock frequency: {int(coreFrequency/2/255)}")
        await self.configureLayerSPIDivider(divider,flush)

    async def configureLayerSPIDivider(self, divider:int , flush = False):
        await self.rfg.write_spi_layers_ckdivider(divider,flush)


    # async def layerSelectSPI(self, layer , cs : bool, flush = False):
    #     """This helper method asserts the shared CSN to 0 by selecting CS on layer 0
    #     it's a helper to be used only if the hardware uses a shared Chip Select!!
    #     If any Layer is in autoread mode, chip select will be already asserted
    #     """
    #     layerCfg = await getattr(self.rfg, f"read_layer_{layer}_cfg_ctrl")()
    #     layerCfg = (layerCfg | (1 << 3)) if cs else (layerCfg & ~(1 << 3))
    #     await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(layerCfg,flush)


    async def layersSetSPICSN(self, cs = False, flush = False):
        """This helper method asserts the shared CSN to 0 by selecting CS on layer 0
        it's a helper to be used only if the hardware uses a shared Chip Select!!
        If any Layer is in autoread mode, chip select will be already asserted
        """
        layer0Cfg = await self.rfg.read_layer_0_cfg_ctrl()
        if cs:
            layer0Cfg = layer0Cfg | (1 << 3)
        else:
            layer0Cfg = layer0Cfg & ~(1 << 3)

        await self.rfg.write_layer_0_cfg_ctrl(layer0Cfg,flush)

    async def layersSelectSPI(self, flush = False):
        """This helper method asserts the shared CSN to 0 by selecting CS on layer 0
        it's a helper to be used only if the hardware uses a shared Chip Select!!
        If any Layer is in autoread mode, chip select will be already asserted
        """
        layer0Cfg = await self.rfg.read_layer_0_cfg_ctrl()
        layer0Cfg = layer0Cfg | (1 << 3)
        await self.rfg.write_layer_0_cfg_ctrl(layer0Cfg,flush)

    async def layersDeselectSPI(self, flush = False):
        """This helper method deasserts the shared CSN to 1 by deselecting CS on layer 0
        it's a helper to be used only if the hardware uses a shared Chip Select!!
        If any Layer is in autoread mode, chip select will stay asserted
        """
        layer0Cfg = await self.rfg.read_layer_0_cfg_ctrl()
        layer0Cfg = layer0Cfg & ~(1 << 3)
        await self.rfg.write_layer_0_cfg_ctrl(layer0Cfg,flush)


    # async def resetLayer(self, layer : int , waitTime : float = 0.5 ):
    #     """Sets Layer in Reset then Remove reset after a wait time. The registers are written right now.

    #     Args:
    #         layer (int): layer to reset
    #         waitTime (float):  Reset duration - Default 0.5s
    #     """
    #     #await self.setLayerReset(layer = layer, reset = True , flush = True )
    #     await self.setLayerConfig(layer=layer, reset=True, autoread=False, hold=False, chipSelect=False, disableMISO=True, flush=True)
    #     await asyncio.sleep(waitTime)
    #     #await self.setLayerReset(layer = layer, reset = False , flush = True )
    #     await self.setLayerConfig(layer=layer, reset=False, autoread=False, hold=False, chipSelect=False, disableMISO=True, flush=True)

    async def resetLayers(self, waitTime: float = 0.5, flush=True):
        """Reset all layers because the reset line is shared.

        Args:
            waitTime (float):  Reset duration - Default 0.5s
        """
        layer0Cfg = await self.rfg.read_layer_0_cfg_ctrl()
        layer0Cfg |= (1<<1)
        await self.rfg.write_layer_0_cfg_ctrl(layer0Cfg,flush)
        await asyncio.sleep(waitTime)
        layer0Cfg &= ~(1<<1)
        await self.rfg.write_layer_0_cfg_ctrl(layer0Cfg,flush)

    async def resetLayersFull(self, waitTime: float = 0.5, flush=True):
        """Reset all layers because the reset line is shared.

        Args:
            waitTime (float):  Reset duration - Default 0.5s
        """
        layersCfg = [await getattr(self.rfg, f"read_layer_{layer}_cfg_ctrl")() for layer in range(3)]
        for layer in range(3):
            layersCfg[layer] |= (1<<1)
            await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(layersCfg[layer], flush)
        await asyncio.sleep(waitTime)
        for layer in range(3):
            layersCfg[layer] &= ~(1<<1)
            await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(layersCfg[layer], flush)

    # @deprecated("Please use clearer setLayerConfig method")
    # async def setLayerReset(self,layer:int, reset : bool, disable_autoread : bool  = True, modify : bool = False, flush = False):
    #     """Asserts/Deasserts the Reset output for the given layer

    #     Args:
    #         disable_autoread (int): By default 1, disables the automatic layer readout upon interruptn=0 condition
    #         modify (bool): Reads the Control register first and only change the required bits
    #         flush (bool): Write the register right away

    #     """
    #     regval = 0xff if reset is True else 0x00
    #     if modify is True:
    #         regval =  await getattr(self.rfg, f"read_layer_{layer}_cfg_ctrl")()

    #     if reset is True:
    #         regval |= (1<<1)
    #     else:
    #         regval &= ~(1<<1)

    #     if disable_autoread is True:
    #         regval |= (1<<2)
    #     else:
    #         regval &= ~(1<<2)

    #     #if not reset: 
    #     #    regval = regval | ( disable_autoread << 2 )
    #     await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(regval,flush)

    async def setLayerConfig(self,layer:int, reset : bool, autoread : bool, hold:bool , chipSelect:bool = False,disableMISO:bool = False, flush = False):
        """Modified the layer config with provided bools
            Since Reset and hold are shared and only connected to layer #0 and CSN is shared and or-ed between layers, you better avoid this command unless you know what you are doing
        Args:
            layer (int): layer to reset
            reset (bool): Assert/deassert reset I/O to ASIC
            autoread (bool): Enables or Disables interrupt-based automatic reading
            hold (bool): Assert/deassert hold I/O to ASIC
            chipSelect (bool): Assert/deassert Chip Select for this layer (I/O is inverted in firmware to produce low-active signal)
            disableMISO (bool): Disable SPI MISO bytes reading. Setting this bit to 1 prevents the Firmware from reading bytes
            flush (bool): Write the register right away

        """
        regval =  await getattr(self.rfg, f"read_layer_{layer}_cfg_ctrl")()

        if reset is True:
            regval |= (1<<1)
        else:
            regval &= ~(1<<1)

        if hold is True:
            regval |= 1 
        else: 
            regval &= 0XFE

        # Autoread is "disable" in config, so True here means False in the register
        if autoread is False:
            regval |= (1<<2)
        else:
            regval &= ~(1<<2)

        if chipSelect is True:
            regval |= (1<<3)
        else:
            regval &= ~(1<<3)

        if disableMISO is True:
            regval |= (1<<4)
        else:
            regval &= ~(1<<4)

        await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(regval,flush)

    # async def holdLayer(self,layer:int,hold:bool = True,flush:bool = False):
    #     """Asserts/Deasserts the hold signal for the given layer - This method reads the ctrl register and modifies it
    #     ACTUALLY does not work for astep because hold is chared
    #     """
    #     ctrl = await getattr(self.rfg, f"read_layer_{layer}_cfg_ctrl")()
    #     if hold:
    #         ctrl |= 1 
    #     else: 
    #         ctrl &= 0XFE
    #     await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(ctrl,flush=flush) 

    async def holdLayers(self, hold:bool, flush:bool = False):
        """
        """
        ctrl = await getattr(self.rfg, f"read_layer_0_cfg_ctrl")()
        if hold:
            ctrl |= 1 
        else: 
            ctrl &= 0XFE
        await getattr(self.rfg, f"write_layer_0_cfg_ctrl")(ctrl,flush=flush)

    async def enableLayersReadout(self, layerlst:list, autoread:bool, flush:bool = False):
        """
        Enables readout for a list of layers:
         - Disable autoread and chipselect for all layers
         - Disable MISO for all layers
         - Enable autoread and chipselect for selected layers
         - Enable MISO for select layers
         - Lower shared hold
        :param layerlst: list of layers numbers (int) for which readout will be enabled
        :param autoread: bool, True for autoread
        :param flush:
        """
        await self.disableLayersReadout(flush=True)
        if 0 in layerlst: await self.setLayerConfig(layer=0, hold=True, reset=False, autoread=autoread, chipSelect=True, disableMISO=False, flush=True)
        if 1 in layerlst: await self.setLayerConfig(layer=1, hold=False, reset=False, autoread=autoread, chipSelect=True, disableMISO=False, flush=True)
        if 2 in layerlst: await self.setLayerConfig(layer=2, hold=False, reset=False, autoread=autoread, chipSelect=True, disableMISO=False, flush=True)
        await self.holdLayers(hold=False, flush=True)
        # regval =  [await getattr(self.rfg, f"read_layer_{layer}_cfg_ctrl")() for layer in range(3)]
        # for layer in range(3):
        #     regval[layer] = (regval[layer] | 0b010100) & 0b110111
        # for layer in layerlst:
        #     regval[layer] = (regval[layer] | 0b001000) & 0b101011 if autoread else (regval[layer] | 0b001100) & 0b101111
        # for layer in range(3):
        #     await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(regval[layer],flush)
        # await self.holdLayers(hold=False, flush=flush)

    async def disableLayersReadout(self, flush:bool = True):
        """
        Disable readout for all layers
         - Raise shared Hold
         - Disable autoread, chipselect and MISO
        """
        await self.setLayerConfig(layer=0, hold=True, reset=False, autoread=False, chipSelect=False, disableMISO=True, flush=flush)
        await self.setLayerConfig(layer=1, hold=False, reset=False, autoread=False, chipSelect=False, disableMISO=True, flush=flush)
        await self.setLayerConfig(layer=2, hold=False, reset=False, autoread=False, chipSelect=False, disableMISO=True, flush=flush)
        # await self.holdLayers(hold=True, flush=flush)
        # regval =  [await getattr(self.rfg, f"read_layer_{layer}_cfg_ctrl")() for layer in range(3)]
        # for layer in range(3):
        #     regval[layer] = (regval[layer] | 0b010100) & 0b110111
        # for layer in range(3):
        #     await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(regval[layer],flush)


    async def writeLayerBytes(self,layer : int , bytes: bytearray,flush:bool = False):
        await getattr(self.rfg, f"write_layer_{layer}_mosi_bytes")(bytes,flush)

    async def writeBytesToLayer(self,layer : int , bytes: bytearray,waitBytesSend : bool = False, flush:bool = False):
        await getattr(self.rfg, f"write_layer_{layer}_mosi_bytes")(bytes,flush)
        if waitBytesSend is True:
            await self.assertLayerNotInReset(layer)
            while (await getattr(self.rfg, f"read_layer_{layer}_mosi_write_size")() > 0):
                pass

    async def getLayerMOSIBytesCount(self,layer:int):
        return await getattr(self.rfg,f"read_layer_{layer}_mosi_write_size")()

    async def getLayerStatIDLECounter(self,layer:int):
        return await getattr(self.rfg, f"read_layer_{layer}_stat_idle_counter")()

    async def getLayerStatFRAMECounter(self,layer:int):
        return await getattr(self.rfg, f"read_layer_{layer}_stat_frame_counter")()

    async def getLayerStatus(self,layer:int):
        return await getattr(self.rfg, f"read_layer_{layer}_status")()

    async def getLayerControl(self,layer:int):
        return await getattr(self.rfg, f"read_layer_{layer}_cfg_ctrl")()

    async def getLayerWrongLength(self, layer:int):
        return await getattr(self.rfg, f"read_layer_{layer}_stat_wronglength_counter")()

    async def zeroLayerWrongLength(self, layer:int, flush:bool =True):
        await getattr(self.rfg, f"write_layer_{layer}_stat_wronglength_counter")(0, flush=flush)


    async def assertLayerNotInReset(self,layer:int):
        ctrlReg = await self.getLayerControl(layer)
        if ((ctrlReg >> 1) & 0x1) == 1:
            raise Exception(f"Layer {layer} is in reset, user requests it is not")

    async def resetLayerStatCounters(self,layer:int,flush:bool = True):
        await getattr(self.rfg, f"write_layer_{layer}_stat_frame_counter")(0,False)
        await getattr(self.rfg, f"write_layer_{layer}_stat_idle_counter")(0,flush)

    async def getLayerMISOBytesCount(self,layer:int):
        """Returns the number of bytes in the Slave Out Bytes Buffer"""
        return await getattr(self.rfg, f"read_layer_{layer}_mosi_write_size")()


    ## Readout
    ################
    async def readoutGetBufferSize(self):
        """Returns the actual size of buffer"""
        return await self.rfg.read_layers_readout_read_size()

    async def readoutReadBytes(self,count : int):
        ## Using the _raw version returns an array of bytes, while the normal method converts to int based on the number of bytes
        return  await self.rfg.read_layers_readout_raw(count = count) if count > 0 else  []


    ## FPGA Timestamp config
    ############

    async def layersConfigFPGATimestamp(self,enable:bool,force : bool,source_match_counter:bool,source_external:bool,flush:bool = False):
        """Configure the FPGA Timestamp to count from the internal match counter, the external TS input or force at each clock cycle"""
        assert not (source_match_counter is True and source_external is True) , "Don't configure FPGA TS to both count from internal match counter or the external clock"
        regVal = 0
        regVal |= 0x0 if enable is False else 0x1
        regVal |= 0x0 if source_match_counter is False else 0x2
        regVal |= 0x0 if source_external is False else 0x4
        regVal |= 0x0 if force is False else 0x8
        await self.rfg.write_layers_cfg_frame_tag_counter_ctrl(regVal,flush)

    async def layersConfigFPGATimestampFrequency(self,targetFrequencyHz:int,flush:bool = False):
        """Configure the internal matching counter to trigger an FPGA Timestmap count with a certain frequency"""
        coreFrequency = self.getFPGACoreFrequency()
        divider = int( coreFrequency / (targetFrequencyHz))
        assert divider >=1 and divider < pow(2,32) , (f"Target Freq is too slow, Divider {divider} is too high, min. clock frequency: {int(coreFrequency/pow(2,32))}")
        await self.rfg.write_layers_cfg_frame_tag_counter_trigger_match(divider,flush)

close() async

Close the Register File I/O Connection to the underlying driver

Source code in drivers/boards/board_driver.py

async def close(self):
    """Close the Register File I/O Connection to the underlying driver"""
    self.openedEvent.clear()
    await self.rfg.io.close()

configureLayerSPIFrequency(targetFrequencyHz, flush=False) async

Calculated required divider to reach the provided target SPI clock frequency

Source code in drivers/boards/board_driver.py

async def configureLayerSPIFrequency(self, targetFrequencyHz : int , flush = False):
    """Calculated required divider to reach the provided target SPI clock frequency"""
    coreFrequency = self.getFPGACoreFrequency()
    divider = int( coreFrequency / (2 * targetFrequencyHz))
    assert divider >=1 and divider <=255 , (f"Divider {divider} is too high, min. clock frequency: {int(coreFrequency/2/255)}")
    await self.configureLayerSPIDivider(divider,flush)

configureLayersFrameTagFrequency(targetFrequencyHz, flush=False) async

Calculated required divider to reach the provided target SPI clock frequency

Source code in drivers/boards/board_driver.py

async def configureLayersFrameTagFrequency(self, targetFrequencyHz : int , flush = False):
    """Calculated required divider to reach the provided target SPI clock frequency"""
    coreFrequency = self.getFPGACoreFrequency()
    divider = int( coreFrequency / ( targetFrequencyHz))
    assert divider >=1 and divider <=255 , (f"Divider {divider} is too high, min. clock frequency: {int(coreFrequency/255)}")
    await self.configureLayersFrameTagDivider(divider,flush)

disableLayersReadout(flush=True) async

Disable readout for all layers - Raise shared Hold - Disable autoread, chipselect and MISO

Source code in drivers/boards/board_driver.py

async def disableLayersReadout(self, flush:bool = True):
    """
    Disable readout for all layers
     - Raise shared Hold
     - Disable autoread, chipselect and MISO
    """
    await self.setLayerConfig(layer=0, hold=True, reset=False, autoread=False, chipSelect=False, disableMISO=True, flush=flush)
    await self.setLayerConfig(layer=1, hold=False, reset=False, autoread=False, chipSelect=False, disableMISO=True, flush=flush)
    await self.setLayerConfig(layer=2, hold=False, reset=False, autoread=False, chipSelect=False, disableMISO=True, flush=flush)

enableLayersReadout(layerlst, autoread, flush=False) async

Enables readout for a list of layers

• Disable autoread and chipselect for all layers
• Disable MISO for all layers
• Enable autoread and chipselect for selected layers
• Enable MISO for select layers
• Lower shared hold

:param layerlst: list of layers numbers (int) for which readout will be enabled :param autoread: bool, True for autoread :param flush:

Source code in drivers/boards/board_driver.py

async def enableLayersReadout(self, layerlst:list, autoread:bool, flush:bool = False):
    """
    Enables readout for a list of layers:
     - Disable autoread and chipselect for all layers
     - Disable MISO for all layers
     - Enable autoread and chipselect for selected layers
     - Enable MISO for select layers
     - Lower shared hold
    :param layerlst: list of layers numbers (int) for which readout will be enabled
    :param autoread: bool, True for autoread
    :param flush:
    """
    await self.disableLayersReadout(flush=True)
    if 0 in layerlst: await self.setLayerConfig(layer=0, hold=True, reset=False, autoread=autoread, chipSelect=True, disableMISO=False, flush=True)
    if 1 in layerlst: await self.setLayerConfig(layer=1, hold=False, reset=False, autoread=autoread, chipSelect=True, disableMISO=False, flush=True)
    if 2 in layerlst: await self.setLayerConfig(layer=2, hold=False, reset=False, autoread=autoread, chipSelect=True, disableMISO=False, flush=True)
    await self.holdLayers(hold=False, flush=True)

enableSensorClocks(flush=False) async

Writes the I/O Control register to enable both Timestamp and Sample clock outputs

Source code in drivers/boards/board_driver.py

async def enableSensorClocks(self,flush:bool = False):
    """Writes the I/O Control register to enable both Timestamp and Sample clock outputs"""
    await self.ioSetSampleClock(enable=True, flush=flush)
    await self.ioSetTimestampClock( enable=True, flush=flush)

flush()

Flushed the RFG instance, use to be sure no bytes are pending writting

Source code in drivers/boards/board_driver.py

def flush(self):
    """Flushed the RFG instance, use to be sure no bytes are pending writting"""
    self.rfg.flush()

getAsic(row=0)

Returns the Asic Model for the Given Row - Other chips in the Daisy Chain are handeled by the returned 'front' model

Source code in drivers/boards/board_driver.py

def getAsic(self,row = 0 ): 
    """Returns the Asic Model for the Given Row - Other chips in the Daisy Chain are handeled by the returned 'front' model"""
    return self.asics[row]

getFPGACoreFrequency()

Returns the Core Clock frequency to help clock divider configuration - this method is overriden by implementation class (Gecco or Cmod)

Source code in drivers/boards/board_driver.py

def getFPGACoreFrequency(self):
    """Returns the Core Clock frequency to help clock divider configuration - this method is overriden by implementation class (Gecco or Cmod)"""
    pass

getLayerMISOBytesCount(layer) async

Returns the number of bytes in the Slave Out Bytes Buffer

Source code in drivers/boards/board_driver.py

async def getLayerMISOBytesCount(self,layer:int):
    """Returns the number of bytes in the Slave Out Bytes Buffer"""
    return await getattr(self.rfg, f"read_layer_{layer}_mosi_write_size")()

holdLayers(hold, flush=False) async

Source code in drivers/boards/board_driver.py

async def holdLayers(self, hold:bool, flush:bool = False):
    """
    """
    ctrl = await getattr(self.rfg, f"read_layer_0_cfg_ctrl")()
    if hold:
        ctrl |= 1 
    else: 
        ctrl &= 0XFE
    await getattr(self.rfg, f"write_layer_0_cfg_ctrl")(ctrl,flush=flush)

ioSetAstropixTSToFPGATS(enable, flush=False) async

The Astropix TS clock can be sourced from the external FPGA TS clock (it true) or from the internal TS clock (if false)

Source code in drivers/boards/board_driver.py

async def ioSetAstropixTSToFPGATS(self,enable:bool,flush:bool = False):
    """The Astropix TS clock can be sourced from the external FPGA TS clock (it true) or from the internal TS clock (if false)"""
    v = await self.rfg.read_io_ctrl()
    if enable: v|=0x20 
    else: v &= ~(0x20)
    await self.rfg.write_io_ctrl(v,flush) 

ioSetFPGAExternalTSClockDifferential(enable, flush=False) async

If an external clock input is used for the FPGA TS counter, it is differential or not

Source code in drivers/boards/board_driver.py

async def ioSetFPGAExternalTSClockDifferential(self,enable:bool,flush:bool = False):
    """If an external clock input is used for the FPGA TS counter, it is differential or not"""
    v = await self.rfg.read_io_ctrl()
    if enable: v|=0x10 
    else: v &= ~(0x10)
    await self.rfg.write_io_ctrl(v,flush)

layersConfigFPGATimestamp(enable, force, source_match_counter, source_external, flush=False) async

Configure the FPGA Timestamp to count from the internal match counter, the external TS input or force at each clock cycle

Source code in drivers/boards/board_driver.py

async def layersConfigFPGATimestamp(self,enable:bool,force : bool,source_match_counter:bool,source_external:bool,flush:bool = False):
    """Configure the FPGA Timestamp to count from the internal match counter, the external TS input or force at each clock cycle"""
    assert not (source_match_counter is True and source_external is True) , "Don't configure FPGA TS to both count from internal match counter or the external clock"
    regVal = 0
    regVal |= 0x0 if enable is False else 0x1
    regVal |= 0x0 if source_match_counter is False else 0x2
    regVal |= 0x0 if source_external is False else 0x4
    regVal |= 0x0 if force is False else 0x8
    await self.rfg.write_layers_cfg_frame_tag_counter_ctrl(regVal,flush)

layersConfigFPGATimestampFrequency(targetFrequencyHz, flush=False) async

Configure the internal matching counter to trigger an FPGA Timestmap count with a certain frequency

Source code in drivers/boards/board_driver.py

async def layersConfigFPGATimestampFrequency(self,targetFrequencyHz:int,flush:bool = False):
    """Configure the internal matching counter to trigger an FPGA Timestmap count with a certain frequency"""
    coreFrequency = self.getFPGACoreFrequency()
    divider = int( coreFrequency / (targetFrequencyHz))
    assert divider >=1 and divider < pow(2,32) , (f"Target Freq is too slow, Divider {divider} is too high, min. clock frequency: {int(coreFrequency/pow(2,32))}")
    await self.rfg.write_layers_cfg_frame_tag_counter_trigger_match(divider,flush)

layersDeselectSPI(flush=False) async

This helper method deasserts the shared CSN to 1 by deselecting CS on layer 0 it's a helper to be used only if the hardware uses a shared Chip Select!! If any Layer is in autoread mode, chip select will stay asserted

Source code in drivers/boards/board_driver.py

async def layersDeselectSPI(self, flush = False):
    """This helper method deasserts the shared CSN to 1 by deselecting CS on layer 0
    it's a helper to be used only if the hardware uses a shared Chip Select!!
    If any Layer is in autoread mode, chip select will stay asserted
    """
    layer0Cfg = await self.rfg.read_layer_0_cfg_ctrl()
    layer0Cfg = layer0Cfg & ~(1 << 3)
    await self.rfg.write_layer_0_cfg_ctrl(layer0Cfg,flush)

layersSelectSPI(flush=False) async

This helper method asserts the shared CSN to 0 by selecting CS on layer 0 it's a helper to be used only if the hardware uses a shared Chip Select!! If any Layer is in autoread mode, chip select will be already asserted

Source code in drivers/boards/board_driver.py

async def layersSelectSPI(self, flush = False):
    """This helper method asserts the shared CSN to 0 by selecting CS on layer 0
    it's a helper to be used only if the hardware uses a shared Chip Select!!
    If any Layer is in autoread mode, chip select will be already asserted
    """
    layer0Cfg = await self.rfg.read_layer_0_cfg_ctrl()
    layer0Cfg = layer0Cfg | (1 << 3)
    await self.rfg.write_layer_0_cfg_ctrl(layer0Cfg,flush)

layersSetSPICSN(cs=False, flush=False) async

This helper method asserts the shared CSN to 0 by selecting CS on layer 0 it's a helper to be used only if the hardware uses a shared Chip Select!! If any Layer is in autoread mode, chip select will be already asserted

Source code in drivers/boards/board_driver.py

async def layersSetSPICSN(self, cs = False, flush = False):
    """This helper method asserts the shared CSN to 0 by selecting CS on layer 0
    it's a helper to be used only if the hardware uses a shared Chip Select!!
    If any Layer is in autoread mode, chip select will be already asserted
    """
    layer0Cfg = await self.rfg.read_layer_0_cfg_ctrl()
    if cs:
        layer0Cfg = layer0Cfg | (1 << 3)
    else:
        layer0Cfg = layer0Cfg & ~(1 << 3)

    await self.rfg.write_layer_0_cfg_ctrl(layer0Cfg,flush)

open() async

Open the Register File I/O Connection to the underlying driver

Source code in drivers/boards/board_driver.py

async def open(self):
    """Open the Register File I/O Connection to the underlying driver"""
    await self.rfg.io.open()
    self.openedEvent.set()

readFirmwareID() async

Returns the raw integer with the firmware id

Source code in drivers/boards/board_driver.py

async def readFirmwareID(self):
    """Returns the raw integer with the firmware id"""
    return await (self.rfg.read_hk_firmware_id())

readFirmwareIDName() async

Source code in drivers/boards/board_driver.py

async def readFirmwareIDName(self):
    """"""
    boards  =  {0xab02: 'Nexys GECCO Astropix v2',0xab03: 'Nexys GECCO Astropix v3',0xac03:"CMOD Astropix v3"}
    boardID =  await (self.readFirmwareID())
    return boards.get(boardID,"Firmware ID unknown: {0}".format(hex(boardID)))

readFirmwareVersion() async

Returns the raw integer with the firmware Version

Source code in drivers/boards/board_driver.py

async def readFirmwareVersion(self):
    """Returns the raw integer with the firmware Version"""
    return (await (self.rfg.read_hk_firmware_version()))

readoutGetBufferSize() async

Returns the actual size of buffer

Source code in drivers/boards/board_driver.py

async def readoutGetBufferSize(self):
    """Returns the actual size of buffer"""
    return await self.rfg.read_layers_readout_read_size()

resetLayers(waitTime=0.5, flush=True) async

Reset all layers because the reset line is shared.

Parameters:

Name	Type	Description	Default
waitTime	float	Reset duration - Default 0.5s	0.5

Source code in drivers/boards/board_driver.py

async def resetLayers(self, waitTime: float = 0.5, flush=True):
    """Reset all layers because the reset line is shared.

    Args:
        waitTime (float):  Reset duration - Default 0.5s
    """
    layer0Cfg = await self.rfg.read_layer_0_cfg_ctrl()
    layer0Cfg |= (1<<1)
    await self.rfg.write_layer_0_cfg_ctrl(layer0Cfg,flush)
    await asyncio.sleep(waitTime)
    layer0Cfg &= ~(1<<1)
    await self.rfg.write_layer_0_cfg_ctrl(layer0Cfg,flush)

resetLayersFull(waitTime=0.5, flush=True) async

Reset all layers because the reset line is shared.

Parameters:

Name	Type	Description	Default
waitTime	float	Reset duration - Default 0.5s	0.5

Source code in drivers/boards/board_driver.py

async def resetLayersFull(self, waitTime: float = 0.5, flush=True):
    """Reset all layers because the reset line is shared.

    Args:
        waitTime (float):  Reset duration - Default 0.5s
    """
    layersCfg = [await getattr(self.rfg, f"read_layer_{layer}_cfg_ctrl")() for layer in range(3)]
    for layer in range(3):
        layersCfg[layer] |= (1<<1)
        await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(layersCfg[layer], flush)
    await asyncio.sleep(waitTime)
    for layer in range(3):
        layersCfg[layer] &= ~(1<<1)
        await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(layersCfg[layer], flush)

selectUARTIO(portPath=None)

This method is common to all targets now, because all targets have a USB-UART Converter available

Source code in drivers/boards/board_driver.py

def selectUARTIO(self,portPath : str | None = None ):
    """This method is common to all targets now, because all targets have a USB-UART Converter available"""
    if (portPath == None):
        import drivers.astep.serial
        port = drivers.astep.serial.selectFirstLinuxFTDIPort()
        if port:
            self.rfg.withUARTIO(port.device)
            return self
        else:
            raise RuntimeError("No Serial Port could be listed")
    else:
        self.rfg.withUARTIO(portPath)
        return self

setLayerConfig(layer, reset, autoread, hold, chipSelect=False, disableMISO=False, flush=False) async

Modified the layer config with provided bools Since Reset and hold are shared and only connected to layer #0 and CSN is shared and or-ed between layers, you better avoid this command unless you know what you are doing Args: layer (int): layer to reset reset (bool): Assert/deassert reset I/O to ASIC autoread (bool): Enables or Disables interrupt-based automatic reading hold (bool): Assert/deassert hold I/O to ASIC chipSelect (bool): Assert/deassert Chip Select for this layer (I/O is inverted in firmware to produce low-active signal) disableMISO (bool): Disable SPI MISO bytes reading. Setting this bit to 1 prevents the Firmware from reading bytes flush (bool): Write the register right away

Source code in drivers/boards/board_driver.py

async def setLayerConfig(self,layer:int, reset : bool, autoread : bool, hold:bool , chipSelect:bool = False,disableMISO:bool = False, flush = False):
    """Modified the layer config with provided bools
        Since Reset and hold are shared and only connected to layer #0 and CSN is shared and or-ed between layers, you better avoid this command unless you know what you are doing
    Args:
        layer (int): layer to reset
        reset (bool): Assert/deassert reset I/O to ASIC
        autoread (bool): Enables or Disables interrupt-based automatic reading
        hold (bool): Assert/deassert hold I/O to ASIC
        chipSelect (bool): Assert/deassert Chip Select for this layer (I/O is inverted in firmware to produce low-active signal)
        disableMISO (bool): Disable SPI MISO bytes reading. Setting this bit to 1 prevents the Firmware from reading bytes
        flush (bool): Write the register right away

    """
    regval =  await getattr(self.rfg, f"read_layer_{layer}_cfg_ctrl")()

    if reset is True:
        regval |= (1<<1)
    else:
        regval &= ~(1<<1)

    if hold is True:
        regval |= 1 
    else: 
        regval &= 0XFE

    # Autoread is "disable" in config, so True here means False in the register
    if autoread is False:
        regval |= (1<<2)
    else:
        regval &= ~(1<<2)

    if chipSelect is True:
        regval |= (1<<3)
    else:
        regval &= ~(1<<3)

    if disableMISO is True:
        regval |= (1<<4)
    else:
        regval &= ~(1<<4)

    await getattr(self.rfg, f"write_layer_{layer}_cfg_ctrl")(regval,flush)

setupASIC(version, row=0, chipsPerRow=1, configFile=None)

Configures one row (aka daisy chain) with a single config file

Parameters:

Name	Type	Description	Default
version	int	int, AstroPix chip version	required
row	int	int, number of the current row, default=0	0
chipsPerRow	int	int, number of chips per row (aka daisy chain), default=1	1
configFile	str | None	srt, path to yaml config file, defaults to None (no configuration applied?)	None

Source code in drivers/boards/board_driver.py

def setupASIC(self, version: int, row: int = 0, chipsPerRow: int=1, configFile: str|None = None):
    """Configures one row (aka daisy chain) with a single config file

    Args:
        version: int, AstroPix chip version
        row: int, number of the current row, default=0
        chipsPerRow: int, number of chips per row (aka daisy chain), default=1
        configFile: srt, path to yaml config file, defaults to None (no configuration applied?)
    """
    asic = Asic(rfg = self.rfg, row = row)
    asic.chipversion = version
    if configFile is not None: 
        asic.load_conf_from_yaml(configFile)
    asic._num_chips = chipsPerRow
    self.asics.append(asic)

setupASICS(version, rows=1, chipsPerRow=1, configFile=None)

Configure one or multiple rows with a single config file

Parameters:

Name	Type	Description	Default
version	int	int, AstroPix chip version	required
rows	int	int, number of rows, default=1	1
chipsPerRow	int	int, number of chips per row (aka daisy chain), default=1	1
configFile	str | None	srt, path to yaml config file, defaults to None (no configuration applied?)	None

Source code in drivers/boards/board_driver.py

def setupASICS(self, version: int , rows: int = 1 , chipsPerRow:int = 1 , configFile : str | None = None):
    """Configure one or multiple rows with a single config file

    Args:
        version: int, AstroPix chip version
        rows: int, number of rows, default=1
        chipsPerRow: int, number of chips per row (aka daisy chain), default=1
        configFile: srt, path to yaml config file, defaults to None (no configuration applied?)
    """
    assert version >=2 and version < 4 , "Only Astropix 2 and 3 Supported"
    if version == 2: 
        self.geccoGetVoltageBoard().dacvalues =  (8, [0, 0, 1.1, 1, 0, 0, 1, 1.100])

    for i in range(rows):
        self.setupASIC(version, row=i, chipsPerRow=chipsPerRow, configFile=configFile)

Register File

Bases: AbstractRFG

Register File Entry Point Class

Source code in fsp/astep24_3l_top/__init__.py

class main_rfg(AbstractRFG):
    """Register File Entry Point Class"""


    class Registers(RFGRegister):
        HK_FIRMWARE_ID = 0x0
        HK_FIRMWARE_VERSION = 0x4
        HK_XADC_TEMPERATURE = 0x8
        HK_XADC_VCCINT = 0xa
        HK_CONVERSION_TRIGGER = 0xc
        HK_STAT_CONVERSIONS_COUNTER = 0x10
        HK_CTRL = 0x14
        HK_ADCDAC_MOSI_FIFO = 0x15
        HK_ADC_MISO_FIFO = 0x16
        HK_ADC_MISO_FIFO_READ_SIZE = 0x17
        SPI_LAYERS_CKDIVIDER = 0x1b
        SPI_HK_CKDIVIDER = 0x1c
        LAYER_0_CFG_CTRL = 0x1d
        LAYER_1_CFG_CTRL = 0x1e
        LAYER_2_CFG_CTRL = 0x1f
        LAYER_0_STATUS = 0x20
        LAYER_1_STATUS = 0x21
        LAYER_2_STATUS = 0x22
        LAYER_0_STAT_FRAME_COUNTER = 0x23
        LAYER_1_STAT_FRAME_COUNTER = 0x27
        LAYER_2_STAT_FRAME_COUNTER = 0x2b
        LAYER_0_STAT_IDLE_COUNTER = 0x2f
        LAYER_1_STAT_IDLE_COUNTER = 0x33
        LAYER_2_STAT_IDLE_COUNTER = 0x37
        LAYER_0_STAT_WRONGLENGTH_COUNTER = 0x3b
        LAYER_1_STAT_WRONGLENGTH_COUNTER = 0x3f
        LAYER_2_STAT_WRONGLENGTH_COUNTER = 0x43
        LAYER_0_MOSI = 0x47
        LAYER_0_MOSI_WRITE_SIZE = 0x48
        LAYER_1_MOSI = 0x4c
        LAYER_1_MOSI_WRITE_SIZE = 0x4d
        LAYER_2_MOSI = 0x51
        LAYER_2_MOSI_WRITE_SIZE = 0x52
        LAYER_0_LOOPBACK_MISO = 0x56
        LAYER_0_LOOPBACK_MISO_WRITE_SIZE = 0x57
        LAYER_1_LOOPBACK_MISO = 0x5b
        LAYER_1_LOOPBACK_MISO_WRITE_SIZE = 0x5c
        LAYER_2_LOOPBACK_MISO = 0x60
        LAYER_2_LOOPBACK_MISO_WRITE_SIZE = 0x61
        LAYER_0_LOOPBACK_MOSI = 0x65
        LAYER_0_LOOPBACK_MOSI_READ_SIZE = 0x66
        LAYER_1_LOOPBACK_MOSI = 0x6a
        LAYER_1_LOOPBACK_MOSI_READ_SIZE = 0x6b
        LAYER_2_LOOPBACK_MOSI = 0x6f
        LAYER_2_LOOPBACK_MOSI_READ_SIZE = 0x70
        LAYERS_CFG_FRAME_TAG_COUNTER_CTRL = 0x74
        LAYERS_CFG_FRAME_TAG_COUNTER_TRIGGER = 0x75
        LAYERS_CFG_FRAME_TAG_COUNTER = 0x79
        LAYERS_CFG_NODATA_CONTINUE = 0x7d
        LAYERS_SR_OUT = 0x7e
        LAYERS_SR_IN = 0x7f
        LAYERS_INJ_CTRL = 0x80
        LAYERS_INJ_WADDR = 0x81
        LAYERS_INJ_WDATA = 0x82
        LAYERS_READOUT = 0x83
        LAYERS_READOUT_READ_SIZE = 0x84
        IO_CTRL = 0x88
        IO_LED = 0x89
        GECCO_SR_CTRL = 0x8a
        HK_CONVERSION_TRIGGER_MATCH = 0x8b
        LAYERS_CFG_FRAME_TAG_COUNTER_TRIGGER_MATCH = 0x8f



    def __init__(self):
        super().__init__()


    def hello(self):
        logger.info("Hello World")



    async def read_hk_firmware_id(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['HK_FIRMWARE_ID'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_hk_firmware_id_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['HK_FIRMWARE_ID'],count = count, increment = True)




    async def read_hk_firmware_version(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['HK_FIRMWARE_VERSION'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_hk_firmware_version_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['HK_FIRMWARE_VERSION'],count = count, increment = True)




    async def read_hk_xadc_temperature(self, count : int = 2 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['HK_XADC_TEMPERATURE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_hk_xadc_temperature_raw(self, count : int = 2 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['HK_XADC_TEMPERATURE'],count = count, increment = True)




    async def read_hk_xadc_vccint(self, count : int = 2 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['HK_XADC_VCCINT'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_hk_xadc_vccint_raw(self, count : int = 2 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['HK_XADC_VCCINT'],count = count, increment = True)




    async def write_hk_conversion_trigger(self,value : int,flush = False):
        self.addWrite(register = self.Registers['HK_CONVERSION_TRIGGER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_hk_conversion_trigger(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['HK_CONVERSION_TRIGGER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_hk_conversion_trigger_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['HK_CONVERSION_TRIGGER'],count = count, increment = True)




    async def read_hk_stat_conversions_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['HK_STAT_CONVERSIONS_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_hk_stat_conversions_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['HK_STAT_CONVERSIONS_COUNTER'],count = count, increment = True)




    async def write_hk_ctrl(self,value : int,flush = False):
        self.addWrite(register = self.Registers['HK_CTRL'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_hk_ctrl(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['HK_CTRL'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_hk_ctrl_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['HK_CTRL'],count = count, increment = False)




    async def write_hk_adcdac_mosi_fifo(self,value : int,flush = False):
        self.addWrite(register = self.Registers['HK_ADCDAC_MOSI_FIFO'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def write_hk_adcdac_mosi_fifo_bytes(self,values : bytearray,flush = False):
        for b in values:
            self.addWrite(register = self.Registers['HK_ADCDAC_MOSI_FIFO'],value = b,increment = False,valueLength=1)
        if flush == True:
            await self.flush()




    async def read_hk_adc_miso_fifo(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['HK_ADC_MISO_FIFO'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_hk_adc_miso_fifo_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['HK_ADC_MISO_FIFO'],count = count, increment = False)




    async def read_hk_adc_miso_fifo_read_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['HK_ADC_MISO_FIFO_READ_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_hk_adc_miso_fifo_read_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['HK_ADC_MISO_FIFO_READ_SIZE'],count = count, increment = True)




    async def write_spi_layers_ckdivider(self,value : int,flush = False):
        self.addWrite(register = self.Registers['SPI_LAYERS_CKDIVIDER'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_spi_layers_ckdivider(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['SPI_LAYERS_CKDIVIDER'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_spi_layers_ckdivider_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['SPI_LAYERS_CKDIVIDER'],count = count, increment = False)




    async def write_spi_hk_ckdivider(self,value : int,flush = False):
        self.addWrite(register = self.Registers['SPI_HK_CKDIVIDER'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_spi_hk_ckdivider(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['SPI_HK_CKDIVIDER'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_spi_hk_ckdivider_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['SPI_HK_CKDIVIDER'],count = count, increment = False)




    async def write_layer_0_cfg_ctrl(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_0_CFG_CTRL'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_layer_0_cfg_ctrl(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_0_CFG_CTRL'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layer_0_cfg_ctrl_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_0_CFG_CTRL'],count = count, increment = False)




    async def write_layer_1_cfg_ctrl(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_1_CFG_CTRL'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_layer_1_cfg_ctrl(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_1_CFG_CTRL'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layer_1_cfg_ctrl_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_1_CFG_CTRL'],count = count, increment = False)




    async def write_layer_2_cfg_ctrl(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_2_CFG_CTRL'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_layer_2_cfg_ctrl(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_2_CFG_CTRL'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layer_2_cfg_ctrl_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_2_CFG_CTRL'],count = count, increment = False)




    async def read_layer_0_status(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_0_STATUS'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layer_0_status_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_0_STATUS'],count = count, increment = False)




    async def read_layer_1_status(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_1_STATUS'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layer_1_status_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_1_STATUS'],count = count, increment = False)




    async def read_layer_2_status(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_2_STATUS'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layer_2_status_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_2_STATUS'],count = count, increment = False)




    async def write_layer_0_stat_frame_counter(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_0_STAT_FRAME_COUNTER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layer_0_stat_frame_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_0_STAT_FRAME_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_0_stat_frame_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_0_STAT_FRAME_COUNTER'],count = count, increment = True)




    async def write_layer_1_stat_frame_counter(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_1_STAT_FRAME_COUNTER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layer_1_stat_frame_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_1_STAT_FRAME_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_1_stat_frame_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_1_STAT_FRAME_COUNTER'],count = count, increment = True)




    async def write_layer_2_stat_frame_counter(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_2_STAT_FRAME_COUNTER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layer_2_stat_frame_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_2_STAT_FRAME_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_2_stat_frame_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_2_STAT_FRAME_COUNTER'],count = count, increment = True)




    async def write_layer_0_stat_idle_counter(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_0_STAT_IDLE_COUNTER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layer_0_stat_idle_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_0_STAT_IDLE_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_0_stat_idle_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_0_STAT_IDLE_COUNTER'],count = count, increment = True)




    async def write_layer_1_stat_idle_counter(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_1_STAT_IDLE_COUNTER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layer_1_stat_idle_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_1_STAT_IDLE_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_1_stat_idle_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_1_STAT_IDLE_COUNTER'],count = count, increment = True)




    async def write_layer_2_stat_idle_counter(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_2_STAT_IDLE_COUNTER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layer_2_stat_idle_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_2_STAT_IDLE_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_2_stat_idle_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_2_STAT_IDLE_COUNTER'],count = count, increment = True)




    async def write_layer_0_stat_wronglength_counter(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_0_STAT_WRONGLENGTH_COUNTER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layer_0_stat_wronglength_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_0_STAT_WRONGLENGTH_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_0_stat_wronglength_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_0_STAT_WRONGLENGTH_COUNTER'],count = count, increment = True)




    async def write_layer_1_stat_wronglength_counter(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_1_STAT_WRONGLENGTH_COUNTER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layer_1_stat_wronglength_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_1_STAT_WRONGLENGTH_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_1_stat_wronglength_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_1_STAT_WRONGLENGTH_COUNTER'],count = count, increment = True)




    async def write_layer_2_stat_wronglength_counter(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_2_STAT_WRONGLENGTH_COUNTER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layer_2_stat_wronglength_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_2_STAT_WRONGLENGTH_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_2_stat_wronglength_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_2_STAT_WRONGLENGTH_COUNTER'],count = count, increment = True)




    async def write_layer_0_mosi(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_0_MOSI'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def write_layer_0_mosi_bytes(self,values : bytearray,flush = False):
        for b in values:
            self.addWrite(register = self.Registers['LAYER_0_MOSI'],value = b,increment = False,valueLength=1)
        if flush == True:
            await self.flush()




    async def read_layer_0_mosi_write_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_0_MOSI_WRITE_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_0_mosi_write_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_0_MOSI_WRITE_SIZE'],count = count, increment = True)




    async def write_layer_1_mosi(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_1_MOSI'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def write_layer_1_mosi_bytes(self,values : bytearray,flush = False):
        for b in values:
            self.addWrite(register = self.Registers['LAYER_1_MOSI'],value = b,increment = False,valueLength=1)
        if flush == True:
            await self.flush()




    async def read_layer_1_mosi_write_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_1_MOSI_WRITE_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_1_mosi_write_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_1_MOSI_WRITE_SIZE'],count = count, increment = True)




    async def write_layer_2_mosi(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_2_MOSI'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def write_layer_2_mosi_bytes(self,values : bytearray,flush = False):
        for b in values:
            self.addWrite(register = self.Registers['LAYER_2_MOSI'],value = b,increment = False,valueLength=1)
        if flush == True:
            await self.flush()




    async def read_layer_2_mosi_write_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_2_MOSI_WRITE_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_2_mosi_write_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_2_MOSI_WRITE_SIZE'],count = count, increment = True)




    async def write_layer_0_loopback_miso(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_0_LOOPBACK_MISO'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def write_layer_0_loopback_miso_bytes(self,values : bytearray,flush = False):
        for b in values:
            self.addWrite(register = self.Registers['LAYER_0_LOOPBACK_MISO'],value = b,increment = False,valueLength=1)
        if flush == True:
            await self.flush()




    async def read_layer_0_loopback_miso_write_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_0_LOOPBACK_MISO_WRITE_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_0_loopback_miso_write_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_0_LOOPBACK_MISO_WRITE_SIZE'],count = count, increment = True)




    async def write_layer_1_loopback_miso(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_1_LOOPBACK_MISO'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def write_layer_1_loopback_miso_bytes(self,values : bytearray,flush = False):
        for b in values:
            self.addWrite(register = self.Registers['LAYER_1_LOOPBACK_MISO'],value = b,increment = False,valueLength=1)
        if flush == True:
            await self.flush()




    async def read_layer_1_loopback_miso_write_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_1_LOOPBACK_MISO_WRITE_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_1_loopback_miso_write_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_1_LOOPBACK_MISO_WRITE_SIZE'],count = count, increment = True)




    async def write_layer_2_loopback_miso(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYER_2_LOOPBACK_MISO'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def write_layer_2_loopback_miso_bytes(self,values : bytearray,flush = False):
        for b in values:
            self.addWrite(register = self.Registers['LAYER_2_LOOPBACK_MISO'],value = b,increment = False,valueLength=1)
        if flush == True:
            await self.flush()




    async def read_layer_2_loopback_miso_write_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_2_LOOPBACK_MISO_WRITE_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_2_loopback_miso_write_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_2_LOOPBACK_MISO_WRITE_SIZE'],count = count, increment = True)




    async def read_layer_0_loopback_mosi(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_0_LOOPBACK_MOSI'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layer_0_loopback_mosi_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_0_LOOPBACK_MOSI'],count = count, increment = False)




    async def read_layer_0_loopback_mosi_read_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_0_LOOPBACK_MOSI_READ_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_0_loopback_mosi_read_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_0_LOOPBACK_MOSI_READ_SIZE'],count = count, increment = True)




    async def read_layer_1_loopback_mosi(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_1_LOOPBACK_MOSI'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layer_1_loopback_mosi_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_1_LOOPBACK_MOSI'],count = count, increment = False)




    async def read_layer_1_loopback_mosi_read_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_1_LOOPBACK_MOSI_READ_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_1_loopback_mosi_read_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_1_LOOPBACK_MOSI_READ_SIZE'],count = count, increment = True)




    async def read_layer_2_loopback_mosi(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_2_LOOPBACK_MOSI'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layer_2_loopback_mosi_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_2_LOOPBACK_MOSI'],count = count, increment = False)




    async def read_layer_2_loopback_mosi_read_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYER_2_LOOPBACK_MOSI_READ_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layer_2_loopback_mosi_read_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYER_2_LOOPBACK_MOSI_READ_SIZE'],count = count, increment = True)




    async def write_layers_cfg_frame_tag_counter_ctrl(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER_CTRL'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_layers_cfg_frame_tag_counter_ctrl(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER_CTRL'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layers_cfg_frame_tag_counter_ctrl_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER_CTRL'],count = count, increment = False)




    async def write_layers_cfg_frame_tag_counter_trigger(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER_TRIGGER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layers_cfg_frame_tag_counter_trigger(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER_TRIGGER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layers_cfg_frame_tag_counter_trigger_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER_TRIGGER'],count = count, increment = True)




    async def write_layers_cfg_frame_tag_counter(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layers_cfg_frame_tag_counter(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layers_cfg_frame_tag_counter_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER'],count = count, increment = True)




    async def write_layers_cfg_nodata_continue(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYERS_CFG_NODATA_CONTINUE'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_layers_cfg_nodata_continue(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_CFG_NODATA_CONTINUE'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layers_cfg_nodata_continue_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_CFG_NODATA_CONTINUE'],count = count, increment = False)




    async def write_layers_sr_out(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYERS_SR_OUT'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_layers_sr_out(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_SR_OUT'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layers_sr_out_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_SR_OUT'],count = count, increment = False)




    async def write_layers_sr_in(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYERS_SR_IN'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_layers_sr_in(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_SR_IN'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layers_sr_in_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_SR_IN'],count = count, increment = False)




    async def write_layers_inj_ctrl(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYERS_INJ_CTRL'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_layers_inj_ctrl(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_INJ_CTRL'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layers_inj_ctrl_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_INJ_CTRL'],count = count, increment = False)




    async def write_layers_inj_waddr(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYERS_INJ_WADDR'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_layers_inj_waddr(self, count : int = 0 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_INJ_WADDR'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layers_inj_waddr_raw(self, count : int = 0 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_INJ_WADDR'],count = count, increment = False)




    async def write_layers_inj_wdata(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYERS_INJ_WDATA'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_layers_inj_wdata(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_INJ_WDATA'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layers_inj_wdata_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_INJ_WDATA'],count = count, increment = False)




    async def read_layers_readout(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_READOUT'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_layers_readout_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_READOUT'],count = count, increment = False)




    async def read_layers_readout_read_size(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_READOUT_READ_SIZE'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layers_readout_read_size_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_READOUT_READ_SIZE'],count = count, increment = True)




    async def write_io_ctrl(self,value : int,flush = False):
        self.addWrite(register = self.Registers['IO_CTRL'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_io_ctrl(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['IO_CTRL'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_io_ctrl_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['IO_CTRL'],count = count, increment = False)




    async def write_io_led(self,value : int,flush = False):
        self.addWrite(register = self.Registers['IO_LED'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_io_led(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['IO_LED'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_io_led_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['IO_LED'],count = count, increment = False)




    async def write_gecco_sr_ctrl(self,value : int,flush = False):
        self.addWrite(register = self.Registers['GECCO_SR_CTRL'],value = value,increment = False,valueLength=1)
        if flush == True:
            await self.flush()


    async def read_gecco_sr_ctrl(self, count : int = 1 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['GECCO_SR_CTRL'],count = count, increment = False , targetQueue = targetQueue), 'little') 


    async def read_gecco_sr_ctrl_raw(self, count : int = 1 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['GECCO_SR_CTRL'],count = count, increment = False)




    async def write_hk_conversion_trigger_match(self,value : int,flush = False):
        self.addWrite(register = self.Registers['HK_CONVERSION_TRIGGER_MATCH'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_hk_conversion_trigger_match(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['HK_CONVERSION_TRIGGER_MATCH'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_hk_conversion_trigger_match_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['HK_CONVERSION_TRIGGER_MATCH'],count = count, increment = True)




    async def write_layers_cfg_frame_tag_counter_trigger_match(self,value : int,flush = False):
        self.addWrite(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER_TRIGGER_MATCH'],value = value,increment = True,valueLength=4)
        if flush == True:
            await self.flush()


    async def read_layers_cfg_frame_tag_counter_trigger_match(self, count : int = 4 , targetQueue: str | None = None) -> int: 
        return  int.from_bytes(await self.syncRead(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER_TRIGGER_MATCH'],count = count, increment = True , targetQueue = targetQueue), 'little') 


    async def read_layers_cfg_frame_tag_counter_trigger_match_raw(self, count : int = 4 ) -> bytes: 
        return  await self.syncRead(register = self.Registers['LAYERS_CFG_FRAME_TAG_COUNTER_TRIGGER_MATCH'],count = count, increment = True)